1. Field of the Invention.
The present invention relates generally to data communications and to clock recovery circuits useful in DS1, DS2 and DS3 telecommunications transmission equipment. The present invention relates specifically to the provision of an improved digital phase-locked loop for replacing analog phase-locked loops which use voltage controlled or tank-tuned oscillators. The present invention also relates to low jitter clock recovery circuits for an Integrated System Digital Network (ISDN) two wire bidirectional telecommunication interface between a telephone central office line terminal and subscriber network terminals, called an ISDN U interface. The invention is also applicable to high and low speed transmission multiplexers and subscriber line interface circuits (SLIC's).
2. Description of the Prior Art.
In the known prior art, digital phase-lock loops required a much higher input clock reference frequency than the desired output frequency to allow small clock phase adjustments to be made at the output. The input clock in such prior art systems is divided down to the required output frequency which can be phase corrected by a minimum of one input clock period. Typically a prior art digital phase-locked loop used in a data clock recovery circuit requires an input reference frequency 10 to 100 times the output clock frequency to provide the desired receiver signal-to-noise performance. For example, a low speed optical fiber telecommunications DS2 receiver with a 13.056 Mhz Manchester data sampling clock would require an input reference frequency of 208.9 Mhz (16 times the sampling clock frequency) to provide +/-4.8 nsec sampling resolution. Manchester encoding is non return-to-zero data which consists of a transition in the middle of each symbol where a one is represented as a + pulse followed by a - pulse and a zero is represented by a - pulse followed by a + pulse (or vice versa).
In a special application, such as an ISDN U interface echo cancelling clock recovery circuit for 80 Kbps, 2B1Q data, a minimum input clock reference frequency of 1000 times the bit rate (80 Mhz) is required to provide adequate cancellation of the transmitted signal and the return echo. 2B1Q data format is well known and consists of two binary bits mapped into one quatenary or four level symbol.
There are several disadvantages in using high (&gt;25 Mhz) instead of low (&lt;25 Mhz) frequency reference clocks for digital phase-locked loops. The high speed interface circuitry required is more costly, consumes more power, and generates more radio frequency interference. Also, the crystals used for the high frequency reference do not operate in the fundamental mode but rather in harmonic modes and are consequently less efficient and more costly. High frequency crystals are also more susceptible to frequency drift due to stray capacitance and humidity. Because of these problems, an analog VCO or tuned tank oscillator is generally used in such high frequency applications even though they require initial adjustment or trimming and drift with temperature.
In the aforementioned cross-referenced application Ser. No. 125,523, a low frequency reference clock is used as does the present invention, but the input clock reference therein must be slightly higher in frequency than the output phase-locked frequency. This can be a limitation in some applications where a standard crystal or external frequency is desired. Also large amounts of jitter cannot be tracked since the advance drift correction per bit time is much smaller than the retard correction. Output jitter is inherent in a high resolution digital phase locked loop to maintain phase-lock since continuous retards must occur.
The center frequency high resolution phase-locked loop of the present invention allows the use of an input frequency which is equal to the desired output phase-locked frequency while yielding output clock phase adjustments as small as two NAND gate propagation delays. For 2.mu. CMOS technology, this is about 4 nsec which is equivalent to a 250 Mhz reference clock with a conventional digital phase-locked loop. A DS2 Manchester data receiver requires only a 13.056 Mhz crystal to provide 4-nsec phase adjustments. An ISDN U interface clock recovery circuit could use a 10.24 Mhz crystal to also provide 4 nsec phase adjustments (1/3125th of a bit period). The 10.24 Mhz phase corrected output is divided by 128 to derive the 80 Khz receive clock. The 10.24 Mhz clock is also used to drive digital signal processing hardware.
The center frequency phase-locked loop of the present invention uses an input clock reference which is centered at the frequency at which phase locking is to occur. This allows the use of standard crystals or available system clocks which are equal to or integer multiples of the phase-locked frequency. Equal advance and retard correction increments about the center frequency improve the ability to track large amounts of jitter such as required on standard telecommunications T1 repeaters. Also an accurate phase shift of the input clock reference can be maintained with no jitter and only occasional phase advance or phase retard corrections.
Digital phase-lock loop circuitry is generally well known in the prior art, as exemplified by U.S. Pat. Nos. 3,585,298, Timing Recovery Circuit with Two Speed Phase Correction; 3,646,452, Second Order Digital Phase-Lock Loop; 3,697,689, Fine Timing Recovery System; 3,777,272, Digital Second-Order Phase-Locked Loop; 4,288,874, Timing Data Reproduction System; and 4,400,817, Method and Means of Clock Recovery in a Received Stream of Digital Data.
A further example of the prior art is the digital phase-lock loop used in the NEC uPD9306/A CMOS hard-disk interface IC. This integrated circuit is described in the NEC Microcomputer Products 1987 Data Book Vol. 2 of 2, pages 6-125, 6-126 and 6-127. A delay line with ten 10 nsec taps is required by the described NEC IC, which is not as cost effective as the present invention and does not provide the resolution possible with the present invention, as ten external leads from the delay line must interface the NEC IC.